In 2026, whispers about the tech giants hint at a smarter silicon story from Google and Tag B. The chatter centers on two new chips designed to run AI models more efficiently. One is a memory processing unit built to work hand in hand with Google’s Tensor Processing Unit, the second a brand‑new TPU crafted specifically for AI workloads. The idea isn’t to topple Nvidia in a single leap, but to add deeper integration between memory and compute. Google has long aimed to broaden the role of its TPUs beyond the traditional GPU crowd. Tag B brings its own flavor of silicon craftsmanship to the table. The Information reported that the teams hope to finalize the MPU design soon and move toward test production in the coming year. As is common with big hardware bets, Reuters could not verify the report, and Google and Marvell did not comment at press time. Still, the vision makes for an interesting read for cloud builders and silicon enthusiasts alike.
Google and Marvell: AI chip duet
What makes this plan compelling is how it targets the data path from memory to AI inference. The memory processing unit would sit between memory controllers and the TPU family, aiming to reduce data transfer bottlenecks and lower latency. In practice, this could translate to faster model loading, quicker inference, and more predictable performance in Google Cloud workloads. Pairing a specialized MPU with a TPU optimized for AI workloads would let Google present an end‑to‑end stack that doesn’t rely solely on general‑purpose GPUs. Tag B’s involvement emphasizes high‑bandwidth, low‑power memory access, the exact plumbing that such workloads demand. The proposed arrangement reads like a modular, end‑to‑end solution rather than a single “silver bullet” chip. The potential benefits extend beyond raw speed: better efficiency could lower operating costs for data centers, a win for cloud customers and investors watching the bottom line.
The broader industry context matters here. Google’s cloud revenue has grown thanks to AI services, and investors are keen to see hardware bets deliver tangible returns. A two‑chip strategy could help demonstrate progress on efficiency and performance, signaling that the company is serious about turning AI ambition into a durable advantage. While Nvidia’s GPUs remain dominant in many AI workflows, a targeted MPU‑plus‑TPU path could carve out a useful niche—especially for workloads where data movement is the bottleneck rather than raw compute. Tag B’s involvement signals readiness to move from concept to testable silicon with a sense of urgency, which could speed up validation cycles and shorten time to customer feedback. In short, this is not a rumor sprint; it’s a careful walk toward a more integrated AI stack.
Reuters’ inability to verify the report is a reminder of how early these conversations can be. Still, the mere existence of talks suggests a willingness to explore more specialized accelerators that fit the cloud’s evolving needs. For software developers and cloud operators, the promise is a cleaner separation of tasks: memory handling handled by MPU, compute workload handled by TPU variants, with software toolchains tuned to the combined design. If these chips make it to market, the ecosystem around them—compilers, libraries, and optimizers—will matter almost as much as the hardware itself. Google and Tag B appear to be testing whether a closer collaboration between memory and AI compute can deliver practical benefits in real workloads.
From a product strategy standpoint, the dual‑chip concept resembles a “two engine” approach rather than a single, monolithic accelerator. It hints at a future where AI platforms are built from modular blocks that can be mixed and matched to fit workloads—from language models running in the cloud to edge AI tasks that require tight energy budgets. If the MPU excels at data staging and memory throughput while the TPU handles the heavy lifting of neural network operations, customers could see more consistent performance across diverse tasks. The result could be a more predictable cost structure for cloud AI and easier lifecycle management for data centers seeking to scale responsibly.
Of course, progress will hinge on several practical hurdles. Hardware co‑design of memory subsystems and AI accelerators demands careful alignment of interfaces, software stacks, and testing regimes. The two companies would need to harmonize memory bandwidth, latency targets, thermal envelopes, and software toolchains—no small feat. There’s also the question of timing: hardware ventures like these require careful roadmaps to avoid misalignment with software updates and customer expectations. Yet the appetite for smarter AI accelerators remains strong, especially among enterprises chasing better efficiency without sacrificing performance. Google’s willingness to explore a collaboration with Tag B underscores a broader industry trend: players are increasingly interdependent, and co‑design is becoming a strategic advantage rather than a niche capability. In this light, the Google‑Tag B plan feels less like a speculative stunt and more like a measured attempt to optimize the stack from memory to model output.
Google and Marvell push two‑chip strategy for TPU
In practical terms, the MPU would act as a specialized data conduit, feeding the TPU units with data at high speed and with predictable timing. The second chip—the TPU—would be tailored to the compute patterns common in large AI models, aiming to squeeze out efficiency when it matters most. If realized, this duo could allow cloud developers to design workloads that lean on the MPU for data preparation and on the TPU for inference and some training tasks. The potential gains include reduced data transfer overhead, lower energy consumption, and tighter integration with software tools. For customers, simpler deployment and improved performance could translate into faster time‑to‑insight and a lower total cost of ownership for AI projects. The plan also aligns with a broader industry drift: accelerators are becoming more specialized, and ecosystems are growing around them. Google, with Tag B supplying the silicon backbone, is framing AI acceleration as a collaborative, design‑forward challenge rather than a lone sprint toward a mythical all‑in‑one chip.
Looking ahead, the rumored two‑chip strategy remains an invitation to watchful optimism. If the MPU and TPU prove viable, they could reshape how cloud AI workloads are structured, giving developers a clearer path to high‑throughput, energy‑efficient inference. The real test will be how software teams adapt to a hardware stack that demands precise data choreography and a disciplined approach to optimization. The potential payoff is meaningful: more predictable performance, better efficiency, and a clear narrative that hardware and software teams can rally around. Google’s ambition here isn’t simply to chase the next trend; it’s to refine the AI acceleration story with a practical, customer‑friendly chassis.
Practical steps for preparedness
- Assess current memory bandwidth and latency in your Google Cloud workloads to identify data-path bottlenecks.
- Consider how an MPU–TPU stack could shift where you optimize software, from data staging to model execution.
- Plan for early access programs or pilot deployments if and when hardware samples become available.
FAQ
- What is a memory processing unit (MPU)? A specialized data conduit that helps move and pre‑process data between memory and AI accelerators, potentially reducing latency.
- Why pair an MPU with a TPU? The combination targets data movement and compute patterns typical of large AI models, aiming to improve efficiency and predictability.
- When might this combination reach customers? Industry chatter suggests prototypes could arrive in the coming year, with broader market adoption depending on validation cycles.
- How could this affect cloud AI costs? by reducing data transfer overhead and enabling more predictable resource usage, which can lower total cost of ownership over time.
Linkback attribution: Special thanks to The Information for the original report detailing the talks between Google and Marvell about AI chips. Original article: https://www.theinformation.com/articles/google-marvell-ai-chips
References
- Original source: ET Telecom: Google and Marvell collaborate on next-gen AI chips
- The Information article: The Information: Google and Marvell AI chips
- Google Cloud TPU overview: Google Cloud TPU